The present invention relates to a method for fabricating a semiconductor device, more specifically a method for fabricating a semiconductor device including the step of forming a device isolation region.
As a process for forming a device isolation region defining an active region in a silicon substrate, STI (Shallow Trench Isolation) is known.
The conventional method for forming a device isolation region by the STI will be explained with reference to FIGS. 9A to 10C. FIGS. 9A to 10C are sectional views illustrating the conventional method for forming a device isolation region by STI.
First, a silicon oxide film 102 is formed as a pad oxide film on a silicon substrate 100 by, e.g., thermal oxidation, and then a silicon nitride film 104 is formed on the silicon oxide film 102 by, e.g., CVD.
Next, the silicon nitride film 104 and the silicon oxide film 102 are patterned by photolithography and dry etching (FIG. 9A).
Next, with the silicon nitride film 104 as the mask, the silicon substrate 100 is etched by, e.g., RIE. Thus, a trench 106 for the device isolation is formed in the silicon substrate 100 (FIG. 9B).
Next, a silicon oxide film 108 is deposited by, e.g., CVD on the entire surface of the silicon substrate 100 with the trench 106 formed in. Then, with the silicon nitride film 104 as the stopper, the silicon oxide film 108 is polished until the surface of the silicon nitride film 104 is exposed by, e.g., CMP to remove the silicon oxide film 108 on the silicon nitride film 104 (FIG. 9C).
Next, by wet etching using, e.g., hot phosphoric acid, the silicon nitride film 104 is removed (FIG. 10A).
Thus, the device isolation region 110 is formed of the silicon oxide film 108 buried in the trench 106. The device isolation region 110 defines an active region 112.
Then, ion implantation for forming a well and a channel in the silicon substrate 100 is conducted. Then, wet etching is conducted as the after-treatment, etc. following the ion implantation. This wet etching removes the silicon oxide film on the silicon substrate 100 in the active region 112, and the upper part of the silicon oxide film 108, and the substrate surface is planarized (FIG. 10B).
Next, a gate insulation film 114 of silicon oxide film is formed by, e.g., thermal oxidation on the silicon substrate 100 with the device isolation region 110 formed in.
Then, a polysilicon film is deposited on the gate insulation film 114 by, e.g., CVD and then patterned by photolithography and dry etching. Thus, a gate electrode 116 of the polysilicon film is formed, extended over the active region 112 and the device isolation region 110 (FIG. 10C).
However, the above-described conventional STI illustrated in FIGS. 9A to 10C has the following disadvantage which will be described below.
As described above, the wet etching conducted as the after-treatment, etc. for the ion implantation removes the upper part of the silicon oxide film 108 to thereby planarize the substrate surface. In the wet etching, the upper part of the silicon oxide film 108 is isotropically etched, and accordingly, as illustrated in FIG. 10B, a recess 118 is formed in the silicon oxide film 108 in the device isolation region 110 along the edge of the active region 112.
Resultantly, in the later step of forming the gate electrode 116, the gate electrode 116 is buried in the recess 118. The part of the gate electrode 116 which is buried in the recess 112 is a cause for the leak current due to the electric field concentration. The part buried in the recess 118 of the gate electrode 116 tends to be imperfectly patterned, which also causes the short circuit between the gate electrodes 116.
A technique for suppressing the generation of such defective configuration of the device isolation region around the edge of the active region is disclosed in, e.g., Japanese published unexamined patent application No. Hei 11-145275 (1999).